Accelerators can be used to help a central processing unit (CPU) process workloads. The workloads often require using data from a CPU cache. The accelerators can write data from the workload executions to random access memory (RAM). In input/output (I/O) coherent mode, transmitting a request to write the data to the RAM and transmitting the data to write to the RAM is routed through an interconnect to the RAM and to the RAM through a coherent domain. The path to request writing data to the RAM and the path for data to be written to the RAM are duplicated to pass from the interconnect to the RAM, from the interconnect to the coherent domains, and then to the RAM. The duplicate the paths from the interconnect to the RAM increase area costs in a device having I/O coherent capabilities. The duplicate paths through the coherent domain can also be less efficient than the path from the interconnect to the RAM. The lower efficient path can incur speed, latency, and/or power penalties.